1. Field of the Invention
The present invention relates to a method for manufacturing a flash memory device, and more specifically, to a method for manufacturing a flash memory device having an NAND type structure.
2. Discussion of Related Art
A semiconductor memory device consists of a cell for storing data therein, and peripheral transistors for transferring an external voltage to the cell so that the cell is driven.
A semiconductor memory device includes an NAND type flash memory device. A plurality of memory cell transistors included in the NAND type flash memory device are connected in a structure called a string. In order to select such a string, a select transistor is required.
The type of the select transistor can be classified into two. The first type includes a drain select transistor for supplying the current of a cell transistor as if it serves as a drain in a common MOSFET. Gates of the drain select transistor are electrically connected one another to form a gate line. Such a gate line becomes a drain select line. The second type includes a source select transistor that serves as a source in a common MOSFET. Gates of the source select transistor are electrically connected one another to form a gate line. Such a gate line becomes a source select line.
FIG. 1 is a layout diagram illustrating a typical NAND type flash memory cell array.
Referring to FIG. 1, a plurality of active regions 101 are formed in parallel in predetermined regions of a semiconductor substrate. An impurity is implanted into the active regions 101. Meanwhile, gate lines such as a drain select line DSL, word lines WLa1 to Wlan and WLb1 to WLbn and a source select line SSL are formed on the semiconductor substrate in a direction vertical to the active regions 101.
As such, the NAND type flash memory cell array is composed of the active regions 101, the drain select line DSL and the source select line SSL.
Meanwhile, since these select transistors are formed at the same time when the flash memory cell is fabricated, a bias has to be applied to a first polysilicon layer corresponding to a floating gate in order for the select transistors to operate normally. As such, in order to apply the voltage to the first polysilicon layer corresponding to the floating gate, a contact process is performed.
In case of an NAND flash cell, the operating speed of the cell is sensitive to a resistance value of a select transistor formed using a contact. Currently, the select transistor formed using the contact consists of only resistance of the first polysilicon layer and resistance of the polysilicon layer is about 70 Ω/sheet to 100 Ω/sheet. Due to the development of a photolithography process, if the size of a cell is reduced, the height of the cell is inevitably limited. For such technological developments, the height of the polysilicon layer must be also reduced. Thus, it is inevitable that resistance of the select transistor continues to increase.
As a result, since resistance of the polysilicon layer is very high, it is required that contacts 102 be formed with a predetermined distance and be applied with a bias. The same is true of the drain select line DSL or the source select line SSL. As such, in order to form the contacts 102, a region where the contacts 102 will be formed in a word line direction must be added. This causes the size of a memory chip to increase and the number of a die manufactured per wafer to decrease. In addition, in order to secure a process margin in a photolithography process, a gap between the select transistor and a neighboring cell has to be increased. This requires an additional region in the bit line direction to further reduce the number of a die manufactured per wafer.
Meanwhile, the threshold voltage of the select transistor must be high so as to prevent degradation in the operating properties of the cell due to the leakage current. As such, in order to make the threshold voltage of a transistor higher than the threshold voltage of a memory cell, an ion implantation process for ion implantation control has to be additionally performed, which increases the process step.